This application relates generally to non-volatile semiconductor memories of the flash memory type, their formation, structure and use.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, USB drives, embedded memory, and Solid State Drives (SSDs) which use an array of flash EEPROM cells. An example of a prior art flash memory system is shown in FIG. 1, in which a memory cell array 1 is formed on a memory chip 12, along with various peripheral circuits such as column control circuits 2, row control circuits 3, data input/output circuits 6, etc.
One popular flash EEPROM architecture utilizes a NAND array, wherein a large number of strings of memory cells are connected through one or more select transistors between individual bit lines and a reference potential. A portion of such an array is shown in plan view in FIG. 2A. Although four floating gate memory cells are shown in each string, the individual strings typically include 16, 32 or more memory cell charge storage elements, such as floating gates, in a column. Control gate (word) lines labeled WL0-WL3 and string selection lines, Drain Select Line, “DSL” and Source Select Line “SSL” extend across multiple strings over rows of floating gates. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard by placing a relatively high voltage on their respective word lines and by placing a relatively lower voltage on the one selected word line so that the current flowing through each string is primarily dependent only upon the level of charge stored in the addressed cell below the selected word line. That current typically is sensed for a large number of strings in parallel, thereby to read charge level states along a row of floating gates in parallel.
The top and bottom of a string connect to a global bit line and a common source line respectively through select transistors (source select transistor and drain select transistor). Select transistors are used to connect NAND strings to control circuits when they are to be accessed, and to isolate them when they are not being accessed. Select transistors may be larger than the transistors that form nonvolatile memory cells and select lines may be wider than word lines. In general, it is desirable to form both word lines (which are relatively narrow) and select lines (which are relatively wide) in the same layer or layers using a common pattern.
At either end of a NAND string there is a contact area formed in the silicon substrate to allow the NAND string to be electrically connected. Contact areas in FIG. 2B are N+ doped areas in the substrate formed by implantation in a P-well. A drain contact formed of metal contacts the contact area on the drain side of the NAND string and a source contact also formed of metal contacts the contact area on the source side of the NAND string. Forming such contacts presents various problems as device sizes scale to ever-smaller dimensions.